In telecom circuits low speed signal paths are commonly mapped into higher speed signal paths to enable the routing of high bandwidth traffic from one node to another node using SONET/SDH framed data. Add/drop multiplexers are often used on the network interface cards to support such mapping and demapping operations. However, demapper circuits typically generate gapped and jittery clocks which conventional circuits are not well adapted to handle. A need continues to exist for an improved technique of dividing a clock signal.